--
-- VHDL Architecture Fietssimulator_lib.txd_transmitter.v
--
-- Created:
--          by - John.UNKNOWN (EPOX)
--          at - 14:54:27 04/15/2009
--
-- using Mentor Graphics HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_txd_transmitter IS
   PORT( 
   start : IN     STD_LOGIC;
   clk   : IN     STD_LOGIC;
   rst   : IN     STD_LOGIC;
   txd   : OUT    STD_LOGIC;
   cts   : OUT    STD_LOGIC
   );
END ENTITY s_txd_transmitter;

--
ARCHITECTURE v OF s_txd_transmitter IS

SIGNAL cntr  : INTEGER RANGE 0 TO 103;
SIGNAL shift : STD_LOGIC;
SIGNAL shr   : STD_LOGIC_VECTOR(8 DOWNTO 0);

BEGIN
  
  cts <= '0';
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        cntr <=  0;
      ELSIF RISING_EDGE(clk) THEN
        
        IF start = '1' OR shift = '1' THEN
          cntr <= 0;
        ELSE
          cntr <= cntr + 1;
      END IF;    
        
      END IF;
    END PROCESS;
    
    
    shift <= '1' WHEN  cntr = 103 ELSE '0'; 
    
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        shr <= (OTHERS => '1');
      ELSIF RISING_EDGE(clk) THEN
        
        IF start = '1'  THEN
          shr <= x"50" & '0';
        ELSIF shift = '1' THEN
          shr <= '1' & shr(8 DOWNTO 1);
      END IF;    
        
      END IF;
    END PROCESS;
    
    
    txd <= shr(0);
  
  
  
  
END ARCHITECTURE v;

